This invention relates generally to a method of activating a liquid crystal display and, in particular, to a display activation method which eliminates crosstalk occurring between adjacent column elements in a liquid crystal display.
Conventional liquid crystal displays include a matrix of liquid crystal display elements. Some conventional displays are classified as passive matrix displays and are activated with high duty cycles and time-division multiplexing. Other conventional displays are classified as active matrix displays and each liquid crystal element, or pixel, includes a switching element having storage capabilities. Active matrix liquid crystal displays employing two terminals, separated by a non-linearly conducting material such as a metal-insulator-metal (MIM) device, require relatively simple manufacturing processes and provide high contrast. A driving circuit for a liquid crystal electro-optical device is described in U.S. Pat. No. 4,560,982, the contents of which are hereby incorporated herein by reference.
A simplified configuration of a MIM active matrix liquid crystal display is shown as a display 200 in FIG. 2(A). An A/D converter 201 of display 200 converts an incoming analog video signal into 4-bits of digital video data (D.sub.0 -D.sub.3). The 4-bits of video data D.sub.0 -D.sub.3 are supplied to a Y driver 202 which produces a data signal to a plurality of column electrodes 205 of a liquid crystal panel 204. Liquid crystal panel 204 is in the form of a sheet having orthogonal electrodes arranged in rows and columns. A plurality of row electrodes 206 of panel 204 for supplying scanning signals are driven by an X driver 203.
A timing controller provides a plurality of timing signals DY, YCL, LP, FR and FGS to Y driver 202. Y driver 202 also receives voltages V.sub.0, V.sub.3, V.sub.4 and V.sub.7 for activating the liquid crystal display.
X driver 203 produces a scanning signal to row electrodes 206 of liquid crystal panel 204. X driver 203 is activated by timing signals DX, XCL and FR from the timing controller. X driver 203 also receives voltages V.sub.0, V.sub.1, V.sub.2, V.sub.5 and V.sub.6 for activating the liquid crystal material. The activating voltages decrease sequentially from V.sub.0 to V.sub.7.
A portion of panel 200, including row electrode 206, column electrode 205, a layer of liquid crystal material 207 and a MIM device 208, is shown in FIG. 2(B). Liquid crystal layer 207 and MIM device 208 are connected in series at each intersection of column electrodes 205 and row electrodes 206. One end of liquid crystal layer 207 is electrically coupled to row electrode 206 and one end of MIM device 208 is electrically coupled to column electrode 205. The current-voltage characteristics of MIM device 208 are shown in FIG. 4. The potential across liquid crystal layer 207 is denoted VLC and the potential across MIM 208 is denoted VM.
FIG. 3 is a circuit diagram for Y driver 202. Y driver 202 includes a plurality of output circuits for energizing column electrodes 205. Each output circuit is identical in configuration to the output circuit for energizing a first output Y0 of a line buffer 302.
A shift register 301 successively delivers shift data signals or start signals to each successive line buffer 302 in response to a shift clock pulse YCL. Buffer 302 includes a plurality of 4-bit memories, such as MOA's of a first line buffer 303. When shift register 301 delivers a shift signal, video data bits D.sub.0 -D.sub.3 are successively stored in the memories and video data about one line is thereby stored.
A second line buffer 304 includes a plurality of 4-bit memories such as MOB's. Video data are transferred from first line buffer 303 to second line buffer 304 in response to latch pulse LP. In this manner, video data D.sub.0 -D.sub.3, which are initially sent serially, are converted into parallel form by second line buffer 304.
The video data from second line buffer 304 are inverted by a plurality of inverters 305 and transmitted to a coincidence circuit 307. The other 4-bit input terminals of coincidence circuit 307 receive 4-bit logic data Q.sub.0 -Q.sub.3 from a 4-bit counter 306 which can be a 4-bit binary counter. Counter 306 is reset by signal RES and counts clock pulses FGS which are provided for producing various grey levels.
When coincidence circuit 307 detects the coincidence of inverted data from second line buffer 304 and logic data from 4-bit counter 306, coincidence circuit 307 sets an SR latch 308 by providing a signal to the S input of latch 308. Latch 308 is reset by signal RES which is input to the R input terminal of latch 308. When Y driver 202 is activated in a conventional manner, signal LP is applied to Y driver 202 at both the LP and RES input terminals of Y driver 202 such that the signals were not independent.
As shown in the timing diagram of FIG. 5, fifteen (15) FGS pulses occur within one LP (RES) time period. When signal LP (RES) is applied to SR latch 308, latch 308 takes a logic level of 0. If the inverted data from second line buffer 308 agrees with the logic data from 4-bit counter 306, SR latch 308 assumes a logic value of 1. The period of signal LP corresponds to one data output period and SR latch 308 is maintained at logic 1 during a period given by: ##EQU1##
Terminals Q and Q of SR latch 308 are electrically coupled to the gate terminals of analog switches 309 and 310 respectively. Signals FR and FR are input to analog switches 311 and 312, respectively. Voltages V.sub.0 and V.sub.7 are applied to switches 311 and 312, respectively. To activate liquid crystal material 207, either voltage V.sub.0 or V.sub.7 is applied to the source terminal of analog switch 310 via switch 314 or switch 313. The drain terminals of analog switches 309 and 310 are connected together and deliver column electrode driving output Y0.
Y driver circuit 202 produces Y signal waveforms as shown in FIG. 5. Voltages V.sub.0 -V.sub.7 assume values as follows: EQU V.sub.0 =Vp EQU V.sub.3 =Vp-Va EQU V.sub.4 =Va EQU V.sub.7 =0
The polarity of the Y signal is inverted every data output period, equal to period Ts. The phase is inverted every successive field which is equal to Ts+Tn. A first field is equal to Ts1+Tn1 and a second field is equal to Ts2+Tn2, etc. Both the ratio of the activating ON voltages Vp and (0) to the non-activating OFF voltages Vp-Va and (Va) is determined during one data output period, depending on the contents of video data D.sub.0 -D.sub.3. Accordingly, the output is pulse width-modulated to provide selected grey levels.
X driver 203 receives either shift data signal DX or a start signal and shift data successively in response to shift clock pulses of signal SCL. The particular column electrode 206 corresponding to the position to which data has been transferred receives the following signal as the scanning signal:
at a selected period, either voltage V.sub.0 or V.sub.1 ; and PA1 during every unselected period, a first voltage level of V.sub.1 and V.sub.5 or a second voltage level of V.sub.2 and V.sub.6.
Voltages V.sub.1 -V.sub.6, shown in FIG. 5, assume values given by: EQU V.sub.1 =Vp-Vb EQU V.sub.2 =Vp-Va+Vb EQU V.sub.5 =Va-Vb EQU V.sub.6 =Vb
The voltage level assumed during a selected period and the voltage level during an unselected period are alternating signals, synchronized with signal FR. During a selected period, the voltage level is in phase with signal FR. During an unselected period, the voltage level is 180.degree. out of phase with signal FR.
For the X signal shown in FIG. 5, voltage V.sub.0 becomes equal to Vp (V.sub.0 =V.sub.p) during selected period Ts.sub.1. The first voltage level is then selected during unselected period Tn.sub.1. After the voltage V.sub.7 becomes null (V.sub.7 =0) during selected period Ts.sub.2, the second voltage level is selected during unselected period Tn.sub.2.
Signal Y-X, shown in FIG. 5, shows variations of the potential at Y electrode 205 with respect to the potential at X electrode 206. The illustrated broken lines indicate the potential at a point located midway between MIM device 208 and liquid crystal display 207, as shown in FIG. 2(B). The hatched portion indicates the effective voltage VLC applied to the liquid crystal. The difference between the Y-X signal and the level represented by the broken line indicates voltage VM applied to MIM device 208.
During selected period Ts.sub.1 or Ts.sub.2, the magnitude of .vertline.Y-X.vertline. is large, as shown in the third and first quadrants of the IM-VM characteristic curve of MIM device 208 (FIG. 4); .vertline.VM.vertline. is large, therefore .vertline.IM.vertline. is also large. Accordingly, electric charge is stored in the liquid crystal 207, resulting in a large value of .vertline.VLC.vertline.. The magnitude of .vertline.VLC.vertline. is determined both by the ratio of potential Va (Vp-Va) and potential 0 (Vp) on the application of Y signal during period Ts.sub.1 or Ts.sub.2. As the percentage of 0 (Vp) increases, .vertline.VLC.vertline. increases.
During unselected periods Tn.sub.1 and Tn.sub.2, the Y-X signal assumes levels Vb(Va-Vb) and (Va-Vb)(-Vb), respectively. Therefore, in the first and third quadrants of FIG. 4, .vertline.VM.vertline. takes smaller values than during selected periods TS.sub.1 and TS.sub.2. Electric current IM and electric discharge from liquid crystal 207 through MIM device 208 are also small. Accordingly, during unselected periods Tn.sub.1 and Tn.sub.2, electric charge is retained. Liquid crystal device 200 is activated almost statically. Hence, a liquid crystal display offering high contrast can be realized.
This conventional activation method has certain drawbacks. FIGS. 6(A), 6(B) and 6(C) depict one example of display provided by a liquid crystal. From row electrode 21 to row (2l+3), the even rows are on, and none of the odd rows are on as shown in FIG. 6(B). The other rows, row 2m and row (2m+1) of column n provide a display of another pattern (e.g. half tone pattern). It is noted that the video data to be displayed in both pixels (2m, n) and (2m+1, n) are the same as shown in FIG. 6(C). Although both display the same video data pixel (2m, n) appears bright, pixel (2m+1, n) appears dark. This phenomenon is caused by crosstalk between the successive rows, beginning from row 21 and ending with row 2l+3. The cause of this crosstalk interference is described below.
FIG. 7 shows output Yn from Y driver 202 and outputs X2m and (X2m+1) from X driver 203. Voltages Yn-X2m and Yn-X2m+1 are applied to pixels (2m, n) and (2m+1, n), respectively.
During selected period Ts, .vertline.VLC.vertline. of the liquid crystal having pixel (2m, n) is large due to pulse width modulation driving. However, during retention period Tn, .vertline.VM.vertline. is small. For this reason, electric charge is retained. During selected period Ts, when rows beginning with row 2l and end with (2l+2) are selected, Yn-X2m remains constant, having a voltage of Va-Vb or -(Va-Vb). This occurs because Yn shifts toward Vp during this selected period. Because row 21 is lit up, video data bits take logic values of 1, 1, 1, 1 and the voltage is Vp. Row (2l+1) is not lit up, i.e., video data bits take on logic values of 0, 0, 0, 0 and the voltage is Va. Consequently, .vertline.VM.vertline. is relatively small. Thus, electric discharge through MIM device 208 is small.
For pixel (2m+1, n), during unselected period Tn, when rows beginning with row 21 and ending with row 21+2 are selected, Yn-X2m+1 remains at a voltage of Vb or -Vb. Therefore, .vertline.VM.vertline. is comparatively large and the amount of electric discharge through MIM device 208 is large.
Although the video data at pixels (2m, n) and (2m+1, n) are common, the effective voltage applied to pixel (2m, n) on the liquid crystal, proportional to the area of the hatched portion is larger than the effective voltage applied to pixel (2m+1, n). Therefore, the two pixels differ in brightness, although the same signal is applied to both pixels in a selected time period.
The signal activating the liquid crystal display 200 is inverted at every line. Consequently, if the driving voltage is inverted every M rows, the pattern of either lit up dots or dots that are not lit up in each M rows appears as crosstalk between the pixels of the same column included in the pattern. Conventional liquid crystal activating methods therefore have inadequacies due to these shortcomings.
Accordingly, it is desirable to provide an improved method of activating a liquid crystal display which avoids the shortcomings of the prior art and provides a clear uniform display that lacks localized contrast variations caused by crosstalk.